module opcdec
	(DATA,
	 branch, decabnz,
	 ioset, loadacc,
	 swait,
	 ramp, rsram, rlta);
input	[3:0]	DATA;
output			branch, decabnz;
output			ioset, loadacc;
output			swait;
output			ramp, rsram, rlta;

reg				branch, decabnz;
reg				ioset, loadacc;
reg				swait;
reg				ramp, rsram, rlta;

parameter	BRANCH=4'b0010, DECABNZ=4'b0011,
			IOSET=4'b0100, LOADACC=4'b0101,
			SWAIT=4'b0110,
			RAMP=4'b1000, RSRAM=4'b1010, RLTA=4'b1100;

always @(DATA)
begin
	case (DATA)
		BRANCH:
		begin
			branch = 1;  decabnz = 0;
			ioset = 0;   loadacc = 0;
			swait = 0;
			ramp = 0;    rsram = 0;    rlta = 0;
		end
		DECABNZ:
		begin
			branch = 0;  decabnz = 1;
			ioset = 0;   loadacc = 0;
			swait = 0;
			ramp = 0;    rsram = 0;    rlta = 0;
		end
		IOSET:
		begin
			branch = 0;  decabnz = 0;
			ioset = 1;   loadacc = 0;
			swait = 0;
			ramp = 0;    rsram = 0;    rlta = 0;
		end
		LOADACC:
		begin
			branch = 0;  decabnz = 0;
			ioset = 0;   loadacc = 1;
			swait = 0;
			ramp = 0;    rsram = 0;    rlta = 0;
		end
		SWAIT:
		begin
			branch = 0;  decabnz = 0;
			ioset = 0;   loadacc = 0;
			swait = 1;
			ramp = 0;    rsram = 0;    rlta = 0;
		end
		RAMP:
		begin
			branch = 0;  decabnz = 0;
			ioset = 0;   loadacc = 0;
			swait = 0;
			ramp = 1;    rsram = 0;    rlta = 0;
		end
		RSRAM:
		begin
			branch = 0;  decabnz = 0;
			ioset = 0;   loadacc = 0;
			swait = 0;
			ramp = 0;    rsram = 1;    rlta = 0;
		end
		RLTA:
		begin
			branch = 0;  decabnz = 0;
			ioset = 0;   loadacc = 0;
			swait = 0;
			ramp = 0;    rsram = 0;    rlta = 1;
		end
		default:
		begin
			branch = 0;  decabnz = 0;
			ioset = 0;   loadacc = 0;
			swait = 0;
			ramp = 0;    rsram = 0;    rlta = 0;
		end
	endcase
end

endmodule